1. Field of the Invention
The present invention relates generally to dynamic random access memories (DRAM), and more particularly, to a method of and circuitry for reading data from a DRAM, wherein the magnitude of difference of potential imparted to a bit line pair, as a result of "H" or "L" data on a selected memory cell when the cell is connected to the bit line pair, is equalized.
2. Description of the Prior Art
Recently, in a dynamic random access memory, from a view point of low power dissipation and fast read operation, peripheral circuitry consisting of complementary metal oxide semiconductor (CMOS) transistors and precharging of a bit line to half of an operating power-supply voltage Vcc or 1/2 Vcc have been a major trend, which is described in, for example, an article by Nicky Chau-Chun Lu et al., entitled "Half-V.sub.DD Bit-Line Sensing Scheme in CMOS DRAM's", IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1980, pp. 451-454.
FIG. 1 is a diagram showing schematically the whole structure of a conventional half-Vcc precharging DRAM.
Referring to FIG. 1, the conventional DRAM comprises a memory cell array 1 in which a plurality of memory cells each having digital information of an "H" or "L" level stored in the form of charges are arranged in a matrix of rows and columns. A row address buffer 2 receiving a row address (A0 to A9) externally applied for generating an internal row address, and a row decoder 3 responsive to an internal row address from the row address buffer 2 for generating a signal for selecting one row in the memory cell array 1, are provided for selecting a word line. A column address buffer 4 receiving a column address externally applied for generating an internal column address and a column decoder 5 responsive to an internal column address from the column address buffer 4 for generating a signal for selecting one column in the memory cell array 1, are also provided with the DRAM for selecting a column or a bit line pair. For communicating data signals with external circuitry, in the DRAM, further provided are a (sense amplifier+I/O (input/output)) block 6 comprising sense amplifiers for sensing and amplifying information on each column (bit line) in the memory cell array 1 and I/O gates responsive to an output of the column decoder 5 for connecting the selected column to a read/write amplifier 7, an input buffer 8 receiving input data D.sub.IN externally applied for applying the same to the read/write amplifier 7, and an output buffer 9 receiving the data from the read/write amplifier 7 for applying output data D.sub.OUT to the exterior. The read/write amplifier 7 amplifies an applied signal and applies the same to a circuit in the subsequent stage.
As peripheral circuits, there are provided row clock generator 10 responsive to a signal RAS (row address strobe) externally applied for generating signals defining timing operations associated with row selection, a write control circuit 12 responsive to a write enable signal WE externally applied for generating a signal designating a read/write operation of the DRAM, and a V.sub.BB generator 13 for generating a voltage V.sub.BB for supplying a precharge voltage of bit lines in the memory cell array 1.
FIG. 1 shows an address multiplexing scheme in which a row address and a column address are applied in a time divisional manner. Operation timing of the row address buffer 2 is provided by the signal RAS, and operation timing of the column address buffer 4 is defined by a signal CAS.
FIG. 2 shows an example of a structure of the memory cell array in the conventional DRAM, showing the structure of a block 100 represented by a broken line shown in FIG. 1. In FIG. 2, only the structure associated with a pair of bit lines BL and BL and two word lines WL.sub.i and WL.sub.i+1 is typically shown.
Referring to FIG. 2, a memory cell 6 for storing digital information of "H" or "L" level in the form of charges comprises a single transistor Tr and a single capacitor C. The memory capacitor C has one electrode (a cell plate) connected to a predetermined potential Vcp and another electrode (a storage node) connected to a drain of the transistor Tr. The transistor Tr has its source connected to the bit line BL and its gate connected to the word line WLi.
In order to differentially amplify a signal voltage on the pair of bit lines BL and BL, the bit line pair is provided with a sense amplifier SA. The sense amplifier SA comprises a pMOS sense amplifier responsive to a sense amplifier activating signal S for boosting a potential on a bit line of a higher potential to a power-supply potential Vcc level and an nMOS sense amplifier responsive to a sense amplifier activating signal S for discharging a potential on a bit line of a lower potential to a ground potential. The pMOS sense amplifier comprises two pMOS transistors P1 and P2 having their gates and drains cross-coupled. The nMOS sense amplifier comprises two nMOS transistors N1 and N2 having their gates and drains cross-coupled.
In order to maintain each of the bit lines BL and BL at a precharge potential V.sub.BB after activation of a word line selected by an external address is completed (or in stand-by state), a precharge/equalize block 30 is provided. The precharge/equalize block 30 comprises an equalizing transistor T1 responsive to an equalize signal EQL for electrically connecting the paired bit lines BL and BL, a precharging transistor T2 responsive to the equalize signal EQL for transmitting to the bit line BL a precharge voltage V.sub.BB from the V.sub.BB generator (see FIG. 1), and a precharging transistor T3 responsive to the equalize signal EQL for transmitting to the bit line BL the precharge potential V.sub.BB from the V.sub.BB generator. The bit lines BL and BL are connected, respectively, to data input/output buses I/O and I/O through transfer gate transistors T4 and T5 which are in turn responsive to a column selecting signal (column decode signal) CD from the column decoder (see FIG. 1) to be turned on.
The sense amplifier activating signals S and S and the equalize signal EQL are generated in response to the signal RAS which is a basic operation timing signal of the DRAM.
Furthermore, the precharge voltage V.sub.BB is generally set to half of the operating power-supply voltage Vcc.
FIGS. 3A to 3C are diagrams showing cross-sectional structure of a memory cell, an electron potential under each portion and a read-out waveform which appears on a bit line, in the conventional dynamic RAM. FIG. 3A shows cross-sectional structure of the memory cell. In FIG. 3A, a memory cell 6 comprises an N.sup.+ type impurity diffusion layer 2 constituting a bit line BL (or BL) formed in a predetermined region on a P type semiconductor substrate 3 and an N.sup.+ type diffusion layer 1 constituting a storage node SN of the memory cell. A transistor portion of the memory cell comprises a gate 5, constituting a word line WL, and the N.sup.+ type impurity diffusion layers 1 and 2. Storage capacitance C of the memory cell comprises a cell plate 4 coupled to a cell plate potential Vcp, an insulating film 9 and the storage node SN. FIG. 3B is a diagram showing electron potentials under the storage node SN, the word line WL and the bit line BL. The electron potential under the storage node SN shows electron potentials formed when the memory cell stores information of the "L" and "H" levels, respectively. The electron potential under the word line WL shows electron potentials formed under the word line when a ground potential GND and Vcc/2+V.sub.TH (where V.sub.TH is a threshold voltage of the transistor Tr of the memory cell) are applied on the word line, respectively. The electron potential under the bit line BL shows an electron potential formed when the bit line BL is precharged to Vcc/2.
FIG. 3C is a diagram showing by an electron potential a read-out waveform generated when information stored in the memory cell is read out to the bit line before sensing (or a sense amplifier is activated). When the memory cell having information of the "L" level is accessed, the electron potential under the bit line is increased by .DELTA.V.sub.LR, with respect to the precharge level. On the other hand, when the memory cell having information of the "H" level is accessed, the electron potential under the bit line is decreased by .DELTA.V.sub.HR, relative to the precharge level.
FIG. 4 is a waveform diagram showing an operation in reading out information of the "H" level in the conventional dynamic RAM shown in FIGS. 1 and 2. Referring now to FIGS. 1 to 4, description is made on an operation for reading out the information of the "H" level in the conventional dynamic RAM. When a signal RAS is rendered active in synchronization with the fall of the external RAS signal which is a basic timing signal of the DRAM, an external address is accepted in the dynamic RAM. When the memory cell stores the information of the "L" level, charges of a ground potential level are stored in the storage node SN. On the other hand, when the memory cell stores the information of the "H" level, charges of a Vcc level are stored therein.
After the RAS signal falls, a single word line is selected in response to the accepted external address and a potential on the selected word line WLi rises by word line driving means included in an output portion of the row decoder. In the case where the memory cell stores the information of the "L" level, electrons start to flow from the memory cell to the bit line BL (it is assumed that BL represents a bit line connected to the selected memory cell) when the potential on the selected word line WLi exceeds V.sub.TH. When the potential on the word line WLi attains Vcc/2+V.sub.TH, all charges stored in the memory cell flow out on the bit line BL, so that the electron potential under the bit line BL is increased by a very small voltage .DELTA.V.sub.LR. On the other hand, as shown in FIG. 4, in the case where the memory cell stores information of the "H" level, electrons start to flow from the bit line BL to the memory cell when the potential on the selected word line WLi exceeds Vcc/2+ V.sub.TH. Since the capacitance of a bit line is sufficiently larger than storage capacitance of a memory cell, the memory cell is filled with electrons. As a result, the electron potential under the bit line BL is decreased by a very small voltage .DELTA.V.sub.HR. On the other hand, a potential on a reference bit line BL paired with the bit line BL does not change at all and remains at a precharge level Vcc/2 because the transistor in the memory cell connected to the reference bit line remains in an off state. The potential Vcc/2 on the reference bit line BL and the potential on the bit line BL to which data is read out are compared by the sense amplifier SA which is activated in response to the rise of the sense amplifier activating signal S (and the fall of the signal S), so that a potential on the bit line of a lower level, of the pair of bit lines BL and BL is amplified to a ground potential GND level and a potential on the bit line of a higher level is amplified to a Vcc level. When the precharge potential on bit lines is Vcc/2, an "L" read-out voltage .DELTA.V.sub.LR and an "H" read-out voltage .DELTA.V.sub.HR are equal to each other.
When an RAS active cycle (the time period during which the signal RAS is at a low level) is completed, information on the bit line, amplified by the sense amplifier SA and then latched thereat, is written to the selected memory cell. Then, a word line driving signal and the sense amplifier activating signals S and S are made inactive, and the equalize signal EQL rises, so that the bit lines are equalized and precharged.
In the foregoing description, the "L" read-out voltage indicates the magnitude of change in potential, utilizing as a reference a precharge level, which appears on the bit line connected to the selected memory cell after the potential on the word line rises and before a sensing operation by activation of the sense amplifier starts, when the selected memory cell stores information of the "L" level. Similarly, the "H" read-out voltage indicates the magnitude of change in potential, utilizing as a reference a precharge level, which appears on the bit line connected to the selected memory cell after the potential on the word line rises and before the sensing operation by activation of the sense amplifier starts, when the selected memory cell has information of the "H" level.
In restoring information in the selected memory cell, writing information in a normal write mode and refreshing information stored in the memory cell in a refresh cycle, information of a full Vcc level can be written to the memory cell by boosting the potential on the word line WLi to more than Vcc+V.sub.TH. In FIG. 4, a broken line represents an example in which the potential on the word line WLi is boosted up to more than Vcc+V.sub.TH and "H" information of the full Vcc level is restored at the end at an RAS active cycle (the time period during which the RAS signal is at the "L" level).
As capacity of the dynamic RAM is increased, the cell structure is being made smaller. At the same time, a junction breakdown voltage, a source/drain breakdown voltage of a transistor, a dielectric breakdown voltage of a gate oxide film or the like are decreased. Thus, in a large capacity DRAM, it becomes difficult to boost the potential on the word line up to more than Vcc+V.sub.TH. Assuming that a voltage of a high level of the word line is a power-supply voltage Vcc, the following problem occurs.
FIGS. 5A and 5B are a diagram showing an electron potential in a memory cell and a diagram showing by an electron potential a read-out waveform, respectively, assuming that the voltage of a high level of the word line is Vcc, in a conventional dynamic RAM. As shown in FIG. 5A, if the level of the word line is boosted only to the Vcc level, only charges of the (Vcc-V.sub.TH) level are stored in the storage node SN in the memory cell when writing "H" information. Thus, the change in electron potential which appears on the bit line when information stored in the memory cell is read out to the bit line is to be as shown in FIG. 5B. More specifically, the "L" read-out voltage .DELTA.V.sub.LR and the "H" read-out voltage .DELTA.V.sub.HR have a relation .DELTA.V.sub.LR &gt;.DELTA.V.sub.HR. As a result an operating margin of the sense amplifier is unbalanced, so that a malfunction of the sense amplifier occurs. For example, the sense amplifier does not correctly amplify a signal voltage on the bit line at the time of sensing operation.
The prior art similar to the structure of the present invention is described in an article by S. Saito et al. entitled "A 1MB CMOS DRAM with Fast Page and Static Column Modes", IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1985, PP. 252-253. This prior art discloses a "complementary capacitor coupled dummy cell" coupled to a dummy word line and a bit line so as to set a reference bit line to a correct midpoint of Vcc in an active cycle. However, in the prior art, a voltage bootstrapped to more than Vcc is applied to the word line. Consequently, the prior art does not consider a problem of imbalance between the "H" read-out voltage and the "L" read-out voltage to occur when a voltage applied to the word line is a power-supply voltage Vcc level.